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3.3 Load and Store Instructions
Load and Store instructions move data between memory and general registers and are all I-type instructions.
The only directly supported addressing mode is base register plus 16-bit signed immediate offset.
With the R3900 Processor Core, the result of a load instruction can be used by the immediately following
instruction. Execution of the following instruction is delayed by hardware interlock until the load result
becomes available. The instruction position immediately following the load instruction is referred to as the
load delay slot . In the case of the LWL (Load Word Left) and LWR (Load Word Right) instructions,
however, it is possible to use the destination register of an immediately preceding load instruction as the
target register of the LWL or LWR instruction.
The access type, which indicates the size of data to be loaded or stored, is determined by the operation code
(op) of the load or store instruction. The target address of a load or store is always the smallest byte address
of the target data byte string, regardless of the access type or endian. This address is the most significant byte
for the big endian format, and the least significant byte for the little endian format.
The position of the accessed data is determined by the access type and the two low-order address bits, as
shown in Table 3-1.
Designating a combination other than those shown in table 3-1 results in an Address Error exception.
Low order Accessed Bytes
Access Type address bits Big Endian Little Endian
1 0 31 0 31 0
word
0 0
triple-byte 0
0
0
1
halfword 0
1
0
0
byte
0
0
1
1
0
1
0
1
Table 3-1. Byte specifications for load and store instructions
3210
210
321
10
32
0
1
2
3
0123
012
123
01
23
0
1
2
3