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Architecture
13
The instruction set supported by all MIPS R-Series processors is listed in Table 2-2. Table 2-3 shows
extended instructions supported by the R3900 Processor Core, and Table 2-4 lists coprocessor 0 (CP0)
instructions.
Table 2-5 shows R3000A instructions not supported by the R3900 Processor Core.
Table 2-2. Instructions supported by MIPS R-Series processors (ISA)
Instruction Description
Load/Store Instructions
LB Load Byte
LBU Load Byte Unsigned
LH Load Halfword
LHU Load Halfword Unsigned
LW Load Word
LWL Load Word Left
LWR Load Word Right
SB Store Byte
SH Store Halfword
SW Store Word
SWL Store Word Left
SWR Store Word Right
Computational Instructions
(ALU Immediate)
ADDI Add Immediate
ADDIU Add Immediate Unsigned
SLTI Set on Less Than Immediate
SLTIU Set on Less Than Immediate Unsigned
ANDI AND Immediate
ORI OR Immediate
XORI XOR Immediate
LUI Load Upper Immediate
(ALU 3-operand, register type)
ADD Add
ADDU Add Unsigned
SUB Subtract
SUBU Subtract Unsigned
SLT Set on Less Than
SLTU Set on Less Than Unsigned
AND AND
OR OR
XOR XOR
NOR NOR