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Architecture
140
DIVU Divide Unsigned DIVU
31 26 25 21 20 16 15 6 5 0
SPECIAL
000000
rs
rt
00000
0
00 0000 0000
DIVU
011011
6 5 5 10 6
Format :
DIVU rs, rt
Description :
This instruction divides the contents of general register rs by the contents of general register rt,
treating both operands as two's complement integers. An integer overflow exception is never
raised. If the divisor is zero, the result is undefined.
Ordinarily, an instruction is placed after this instruction to check for zero division.
When an attempt is made to read the division result using MFHI, MFLO, MADD or MADDU before
the divide operation is completed, the read operation is delayed by an interlock.
Divide operations are executed in an independent ALU and can be carried out in parallel with the
execution of other instructions. For this reason, the ALU can continue executing instructions even
during a cache miss or other delay cycle in which ordinary instructions cannot be processed.
Upon completion of the operation, the quotient word is loaded into special register LO, and the
remainder word into special register HI.
If either of the two preceding instructions is MFHI, MFLO, MADD or MADDU, the results of those
instructions are undefined. For the DIVU operation to be carried out correctly, reads of HI or LO
must be separated from writes by two or more instructions.
Operation :
T − 2:
T − 1:
T:
LO ← undefined
HI ← undefined
LO ← undefined
HI ← undefined
LO ← (0 || GPR[rs]) div (0 || GPR[rt])
HI ← (0 || GPR[rs]) mod (0 || GPR[rt])
Exceptions :
None