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Architecture
3
Chapter 1 Introduction
1.1 Features
The R3900 Processor Core is a high-performance 32-bit microprocessor core developed by Toshiba based on
the R3000A RISC (Reduced Instruction Set Computer) microprocessor. The R3000A was developed by
MIPS Technologies, Inc.
Toshiba develops ASSPs (Application Specific Standard Products) using the R3900 Processor Core and
provides the R3900 as a processor core in Embedded Array or Cell-based ICs. The low power consumption
and high cost-performance ratio of this processor make it especially well-suited to embedded control
applications in products such as PDAs (Personal Digital Assistants) and game equipment.
1.1.1 High-performance RISC techniques
• R3000A architecture
− R3000A upward compatible instruction set (excluding TLB (translation lookaside buffer)
instructions and some coprocessor instructions)
− Five-stage pipeline
• Built-in cache memory
− Separate instruction and data caches
− Data cache snoop function: Invalidatation of data in the data cache to maintain cache memory
and main memory consistency on DMA transfer cycles
• Nonblocking load
− Execute the following instruction regardless of a cache miss caused by a preceding load
instruction
• DSP function
− Multiply/Add (32-bit x 32-bit + 64-bit) in one clock cycle.
1.1.2 Functions for embedded applications
• Small code size
− Branch Likely instruction:The branch delay slot accepts an instruction to be executed at the
branch target
− Hardware Interlock: Stall the pipeline at the load delay slot when the instruction in the slot
depends on the data to be loaded