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TMPR3901F
205
Address
Protection
Unit
Debug
Support
Unit
R3900 Processor Core
1KB
Data
Cache
4KB
Instruction
Cache
CPU core
Bus Controller / Write Buffer
System
Interface
Interrupt
Reset
Real-time
Debugger
Interface
Synchroni-
zer
Clock
Generator
Chapter 2 Configuration
This chapter describes the configuration of the TMPR3901F. A block diagram of the TMPR3901F is shown in
Figure 2-1.
2.1 R3900 Processor Core
This is a microprocessor core developed by Toshiba based on the R3000A. (See chapter 2, "Architecture, " in
this manual). Specifications of the TMPR3901F differ somewhat from those of the R3900 Processor Core.
Following are the limitations and modifications made to the R3900 Processor Core.
2.1.1 Instruction Iimitations
The COPz, CTCz and MTCz instructions are treated as NOPs (no operation) by the R3900, and
instructions CFCz and MFCz load undefined data to general-purpose register (rt) in the TMPR3901F.
The TMPR3901F supports four coprocessor condition branch instructions: BCzT, BCzF, BCzTL and
BCzFL. Condition branch signal CPCOND[3:1] can be used with these instructions.
Figure 2-1 TMPR3901F block diagram