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143
JALR Jump And Link Register JALR
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000
rs
0
00000
rd
0
00000
JALR
001001
6 5 5 5 5 6
Format :
JALR rs
JALR rd, rs
Description :
Causes the program to jump unconditionally to the address in general register rs after a delay of one
instruction cycle. The address of the instruction following the delay slot is put in general register rd
as the return address from the jump. If rd is omitted from the assembly language instruction, r31 is
used as the default value.
Register specifiers rs and rd must not be equal, since such an instruction would not have the same
result if re-executed. This error is not trapped, however, the result is undefined.
Since instructions must be aligned on a word boundary, the two low-order bits of the value in target
register rs must be 00. If not, an Address Error exception will be raised when the target instruction
is fetched.
Operation :
T:
T + 1:
temp ← GPR[rs]
GPR[rd] ← PC + 8
PC ← temp
Exceptions :
None