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Architecture
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(3) Lock bit clearing
13 12 11 10 9 8
IALo DALo IALp DALp IALc DALc
exception raised 0 0
IALo DALo IALp DALp IALc DALc
13 12 11 10 9 8
IALo DALo IALp DALp IALc DALc
RFE executed
IALo DALo IALp DALp IALc DALc
IALo,IALp and IALc are reserved for the instruction cache.
The lock bit for an entry is cleared using the CACHE instruction IndexLockBitClear. Clearing
the lock bit disables the lock function.
Clear the lock bit as follows when data written to a locked line should be stored in main
memory.
1) Read the locked data from cache memory
2) Clear the lock bit
3) Store the data that was read
Figure 7-5. Auto-lock bits
Cache register