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Chapter 3 Instruction Set Overview
This chapter summarizes each of the R3900 Processor Core instruction types in table format and explains each
instruction briefly. Details of individual instructions are given in Appendix A.
3.1 Instruction Formats
Each of the R3900 Processor Core instructions is aligned on a word boundary and has a 32-bit (single-word)
length. There are only three instruction formats, as shown in Figure 3-1. As a result, instruction decoding
is simplified. Less frequently used and more complex functions or addressing modes can be realized by
combining these instructions.
31 26 25 21 20 16 15 0
op rs rt immediate
31 26 25 0
op target
31 26 25 21 20 16 15 11 10 6 5 0
op rs rt rd sa funct
op Operation code (6 bits)
rs Source register (5 bits)
rt Target (source or destination) register, or branch condition (5 bits)
rd Destination register (5 bits)
immediate Immediate, branch displacement, address displacement (16 bits)
target Branch target address (26 bits)
sa Shift amount (5 bits)
funct Function (6 bits)
Figure 3-1. Instruction Formats and subfield mnemonics
3.2 Instruction Notation
All variable subfields in the instruction formats used here are written in lower-case letters (rs, rt, immediate,
etc.). Also, an alias is sometimes used for a subfield name, for the sake of clarity. For example, rs in a
load/store instruction may be referred to as “base”. When such an alias refers to a subfield that can take a
variable value, it is likewise written in lower-case letters.
With specific instructions, the instruction subfields “op” and “funct” have fixed 6-bit values. These values
are thus written as equates in upper-case letters. In the Load Byte instruction, for example, op = LB; and in
the ADD instruction, op = SPECIAL and function = ADD.
I-type (Immediate)
J-type (Jump)
R-type (Register)