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Architecture
37
(d) BCzTL, BCzFL (ISA Extended Set)
Instruction Format and Description
Branch on
Coprocessor
z True Likely
BCzTL offset
Generate the branch target address by adding the address of the instruction in
the delay slot (the instruction to be executed during the branch) and the 16-bit
offset (after left-shifting two bits and sign-extending to 32 bits). If the
coprocessor z condition line is true, branch to the target address after a one-
cycle delay. If the condition line is false, nullify the instruction in the delay slot.
Branch on
Coprocessor
z False Likely
BCzFL offset
Generate the branch target address by adding the address of the instruction in
the delay slot (the instruction to be executed during the branch) and the 16-bit
offset (after left-shifting two bits and sign-extending to 32 bits). If the
coprocessor z condition line is false, branch to the target address after a one-
cycle delay. If the condition line is true, nullify the instruction in the delay slot.
offsetfunctop