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CONTENTS
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CONTENTS
Architecture
Chapter 1 Introduction--------------------------------------------------------------------------- 3
1.1 Features ------------------------------------------------------------------------------ 3
1.1.1 High-performance RISC techniques ---------------------------------------------------- 3
1.1.2 Functions for embedded applications--------------------------------------------------- 3
1.1.3 Low power consumption ------------------------------------------------------------------- 4
1.1.4 Development environment for embedded arrays and cell-based ICs ---------- 4
1.2 Notation Used in This Manual--------------------------------------------------- 5
Chapter 2 Architecture ------------------------------------------------------------------------- 7
2.1 Overview------------------------------------------------------------------------------ 7
2.2 Registers------------------------------------------------------------------------------ 8
2.2.1 CPU registers--------------------------------------------------------------------------------- 8
2.2.2 System control coprocessor (CP0) registers ----------------------------------------- 9
2.3 Instruction Set Overview------------------------------------------------------------10
2.4 Data Formats and Addressing ----------------------------------------------------15
2.5 Pipeline Processing Overview-----------------------------------------------------18
2.6 Memory Management Unit (MMU)-----------------------------------------------19
2.6.1 R3900 Processor Core operating modes----------------------------------------------- 19
2.6.2 Direct segment mapping -------------------------------------------------------------------- 20
Chapter 3 Instruction Set Overview------------------------------------------------------------23
3.1 Instruction Formats ------------------------------------------------------------------23
3.2 Instruction Notation ------------------------------------------------------------------23
3.3 Load and Store Instructions -------------------------------------------------------24
3.4 Computational Instructions---------------------------------------------------------27
3.5 Jump/Branch Instructions ----------------------------------------------------------32
3.6 Special Instructions ------------------------------------------------------------------35
3.7 Coprocessor Instructions -----------------------------------------------------------36
3.8 System Control Coprocessor (CP0) Instructions -----------------------------38