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TMPR3901F
201
Chapter 1 Introduction
This document describes the specifications of the TMPR3901F microprocessor. The R3900 Processor Core
is incorporated into the TMPR3901F.
1.1 Features
The TMPR3901F is a general-purpose microprocessor incorporating on-chip the 32-bit R3900 Processor Core,
developed by Toshiba. In addition to the processor core it includes a clock generator, bus interface unit,
memory protection unit and debug support unit.
The TMPR3901F features are as follows.
(1) R3900 Processor Core.
• Developed by Toshiba based on the MIPS Technologies, Inc. RISC architecture.
• Adds the following enhancements to the R3000A for optimal use in embedded applications.
− Pipeline improvements
− Faster multiply operations
− Addition of multiply/add operation instructions
− Addition of Branch Likely instructions
− Addition of debug support functions
− Built-in cache memory (instruction: 4Kbytes, data: 1Kbyte)
(2) On-chip peripheral circuits
• Clock generator (internal 4x-frequency PLL; connection to crystal oscillator)
• Bus interface unit (separate 32-bit address/data bus; 4-level write buffer)
• Memory protection unit
• Debug support unit
(3) Bus interface for ease of system implementation
• Separate 32-bit address/data buses
• Single-read/single-write/burst-read bus operations
• Half-speed bus mode supported
• Operates on internal PLL clock generator and quarter-frequency crystal oscillator
• Bus arbitration and cache snoop functions, to facilitate implementation of external DMAC
• 5 V tolerant input