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instruction in the delay slot is executed during the jump).
The following notes apply to Table 3-10.
• The target address of a branch instruction is generated by adding the address of the instruction in the delay
slot (the instruction to be executed during the branch) to the 16-bit offset (that has been left-shifted two bits
and sign-extended to 32 bits). Branch instructions are executed with a one-cycle delay.
• In the case of the Branch Likely instructions in Table 3-10, if the branch condition is not met and the branch
is not taken, the instruction in the delay slot is treated as a NOP.
Table 3-10. Branch instructions
(a) BEQ, BNE
Instruction Format and Description
Branch on
Equal
BEQ rs, rt, offset
Branch to the target if the contents of registers rs and rt are equal.
Branch on Not
Equal
BNE rs, rt, offset
Branch to the target if the contents of registers rs and rt are not equal.
(b) BLEZ, BGTZ
Instruction Format and Description
Branch on
Less Than or
Equal Zero
BLEZ rs, offset
Branch to the target if register rs is 0 or less.
Branch on
Greater Than
Zero
BGTZ rs, offset
Branch to the target if register rs is greater than 0.
(c) BLTZ, BGEZ, BLTZAL, BGEZAL
Instruction Format and Description
Branch on
Less Than
Zero
BLTZ rs, offset
Branch to the target if register rs is less than zero
Branch on
Greater Than
or Equal Zero
BGEZ rs, offset
Branch to the target if register rs is 0 or greater.
Branch on
Less Than
Zero And Link
BLTZAL rs, offset
Store in r31 (link register) the address of the instruction following the instruction
in the delay slot (the one to be executed during the branch). If register rs is less
than 0, branch to the target.
Branch on
Greater Than
or Equal Zero
And Link
BGEZAL rs, offset
Store in r31 (link register) the address of the instruction following the instruction
in the delay slot (the instruction in the delay slot is executed during the branch).
If register rs is 0 or greater, branch to the target.
rs
rs
rs
offset
offset
offset
rt
0
funct
op
op
op