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CONTENTS
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Chapter 4 Pipeline Architecture-----------------------------------------------------------------39
4.1 Overview--------------------------------------------------------------------------------39
4.2 Delay Slot-------------------------------------------------------------------------------40
4.2.1 Delayed load----------------------------------------------------------------------------------- 40
4.2.2 Delayed branching---------------------------------------------------------------------------- 40
4.3 Nonblocking Load Function --------------------------------------------------------41
4.4 Multiply and Mupliply/Add Instructions (MULT, MULTU, MADD, MADDU) --41
4.5 Divide Instruction (DIV, DIVU) ----------------------------------------------------42
4.6 Streaming-------------------------------------------------------------------------------42
Chapter 5 Memory Management Unit (MMU)-----------------------------------------------43
5.1 R3900 Processor Core Operating Modes--------------------------------------43
5.2 Direct Segment Mapping -----------------------------------------------------------44
Chapter 6 Exception Processing ---------------------------------------------------------------47
6.1 Overview--------------------------------------------------------------------------------47
6.2 Exception Processing Registers--------------------------------------------------50
6.2.1 Cause register --------------------------------------------------------------------------------- 51
6.2.2 EPC (Exception Program Counter) register-------------------------------------------- 52
6.2.3 Status register --------------------------------------------------------------------------------- 53
6.2.4 Cache register --------------------------------------------------------------------------------- 56
6.2.5 Status register and Cache register mode bit and exception processing -------- 58
6.2.6 BadVAddr (Bad Virtual Address) register----------------------------------------------- 60
6.2.7 PRId (Processor Revision Identifier) register------------------------------------------ 60
6.2.8 Config (Configuration) register ------------------------------------------------------------ 61
6.3 Exception Details ---------------------------------------------------------------------63
6.3.1 Memory location of exception vectors --------------------------------------------------- 63
6.3.2 Address Error exception -------------------------------------------------------------------- 64
6.3.3 Breakpoint exception------------------------------------------------------------------------- 65
6.3.4 Bus Error exception -------------------------------------------------------------------------- 66