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Architecture
101
Jump and Branch Instructions
All jump and branch instructions are executed with a delay of one instruction cycle. This means that the
immediately following instruction (the instruction in the delay slot) is executed while the branch target
instruction is being fetched. A jump or branch instruction should never be put in the delay slot; if this is
done, it will not be detected as an error and the result will be undefined.
If an exception or interrupt prevents the delay slot instruction from being completed, the EPC register is set by
hardware to point to the preceding jump or branch instruction. Upon returning from the exception or
interrupt, both the jump/branch instruction and the instruction in the delay slot are executed.
Jump and branch instructions are sometimes restarted after exceptions or interrupts, so they must be made
restartable. When a jump or branch instruction stores a return address value, general-purpose register r31
must not be used as the source register.
Since instructions must be aligned on a word border, the lower two bits of the register value used as an address
with a Jump Register instruction or a Jump And Link Register must be 00. If not, an Address Error exception
will be raised when the target instruction is fetched.