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6.3.6 Interrupts
• Cause
− An Interrupt exception is raised by any of eight interrupts (two software and six hardware). A
hardware interrupt is raised when the interrupt signal goes active. A software interrupt is raised
by setting the Sw1 or Sw0 bits in the Cause register.
• Exception mask
− Each of the eight interrupts can be masked individually by clearing its corresponding bit in the
IntMask field of the Status register.
− All interrupts can be masked by clearing the Status register IE bit to 0.
• Processing
− The common exception vector (0x8000 0080) is used.
− Int(0) is set for ExcCode in the Cause register.
− The Cause register IP and Sw fields indicate the status of current interrupt requests. It is
possible for more than one of these bits to be set or for none to be set (when an interrupt is
asserted and then de-asserted before the register is read).
Notes : You should disable interrupts when executing the RFE instruction because the Status
register contents will be undefined when an interrupt occurs while executing the RFE
instruction.
• Servicing
An interrupt condition set by one of the two software interrupts can be cleared by clearing the
corresponding Cause register bit (Sw1 or Sw0) to 0.
For hardware-generated interrupts, the condition can only be cleared by determining and
handling the source of the corresponding active signal.
The IP field indicates the status of interrupt signals regardless of the Status register IntMask
field. The cause of an interrupt should be determined from a logical AND of the IP and IntMask
fields.
− The EPC register points to the address of the instruction causing an exception. If, however, that
instruction is in the branch delay slot (for execution during a branch), the immediately preceding
branch instruction address is retained in the EPC register and the Cause register BD bit is set to
1.