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6.4 Priority of Exceptions
More than one exception may be raised for the same instruction, in which case only the exception with the
highest priority is reported. The R3900 Processor Core instruction exception priority is shown in Table 6-5.
See chapter 8 for the priority of debug exceptions.
Table 6-5. Priority of Exceptions
Priority Exception (Mnemonic)
High Reset
s
IBE (instruction fetch)
DBE (data access)
NmI
AdEL (instruction fetch)
TLBL (instruction fetch)
CpU
Ov, Sys, Bp, RI
AdEL (load instruction)
AdES (store instruction)
TLBL (data load)
TLBS (store instruction)
t
Mod
Low Int
6.5 Return from Exception Handler
An example of returning from an exception handler is shown below.
MFC0 r27, EPC (store return address in general register)
JR r27 (jump to return address)
RFE (execute RFE instruction in branch delay slot)