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7.3 Cache Test Function
(1) Cache disabling
The Config register bits ICE (Instruction Cache Enable) and DCE (Data Cache Enable) are used to
enable and disable the instruction cache and data cache, respectively.
When a cache is disabled, all cache accesses are misses and there is no refill (nor is there any burst
bus cycle; this is the same as accessing a non-cacheable area). The valid bit (V) for each entry
cannot be modified.
(2) Cache flushing
Both the instruction cache and data cache are flushed when a Reset exception is raised (all valid bits
are cleared to 0).
The instruction cache is flushed by the CACHE instruction IndexInvalidate. The data cache is
flushed by the CACHE instruction HitInvalidate.
Note : An instruction cache IndexInvalidate operation is possible only when the instruction cache is
disabled (Config register ICE bit = 0).
Additional explanation : As a sure way of disabling the instruction cache, streaming should be
stopped by inserting a branch instruction after MTC0, as shown below.
Example:
MTC0 Rn, Config (clear ICE to 0)
J L1 (branch to L1; stop streaming)
NOP (branch delay slot)
L1: CACHE IndexInvalidate, offset (base)
(3) Lock bit clearing
The data cache lock bit is cleared by a Reset exception.
It can also be cleared by the CACHE instruction IndexLockClear. (The IndexLockClear instruction
is reserved for clearing instruction cache lock bits.)