Toshiba TX39 Computer Hardware User Manual


 
Architecture
67
6.3.4 Bus Error exception
Causes
This exception is raised when a bus error signal is input to the R3900 Processor Core during a
memory bus cycle.
This occurs during execution of the instruction causing the bus error. The memory bus cycle
ends upon notification of a bus error. When a bus error is raised during a burst refill, the
following refill is not performed.
A bus error request made by asserting a bus error signal will be ignored if the R3900 Processor
Core is executing a cycle other than a bus cycle. It is therefore not possible to raise a Bus Error
exception in a write access using a write buffer. A general interrupt must be used instead.
Exception mask
The Bus Error exception is not maskable.
Applicable instructions
LB, LBU, LH, LHU, LW, LWL, LWR, SB, SH, SW, SWL, SWR; any fetch instruction.
Processing
The common exception vector (0x8000 0080) is used.
IBE(6) or DBE(7) is set for ExcCode in the Cause register.
The EPC register will have an undefined value except in the following cases.
(1) A SYNC instruction follows execution of a load instruction.
(2) An instruction that follows execution of a load instruction while one-word data cache
refill size is in effect, or that follows a load instruction that loads data from an uncached
area, needs to use the result of the load.
In the above case, since the load delay slot instruction will stall until the end of the read
operation, the EPC will contain the load delay slot address when a bus error occurs.
Note : When the destination address of a load instruction is r0 and the following instruction
uses r0, the R3900 Processor Core will not stall.
The R3900 Processor Core stores the Status register bits KUp, IEp, KUc and IEc in KUo, IEo,
KUp and IEp, respectively, and clears the KUc and IEc bits to 0.
And, the R3900 Processor Core stores Cache register bits DALp, IALp, DALc and IALc in
DALo, IALo, DALp and IALp, respectively, and clears the DALc and IALc bits to 0.
The R3900 Processor Core does not store the cache block in cache memory if the block includes
a word for which a bus error occurred.