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Architecture
145
LB Load Byte LB
31 26 25 21 20 16 15 0
LB
100000
base rt
offset
6 5 5 16
Format :
LB rt, offset(base)
Description :
Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents
of general-purpose register base. It then sign-extends the byte at the memory location pointed to by
the effective address and loads the result into general-purpose register rt.
Operation :
T:
vAddr ← ((offset
15
)
16
||
offset
15..0
)
+ GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
31..2
|| (pAddr
1..0
xor ReverseEndian
2
)
mem ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr
1..0
xor BigEndianCPU
2
GPR[rt] ←(mem
7+8*byte
)
24
|| mem
7+8byte..8*byte
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
Address Error exception