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TMPR3901F
214
(4) CPCOND[3:1]
The CPCOND[3:1] signal is synchronized with the processor clock in phase with SYSCLK (Figure 2-
6).
CPCOND*(external)
CPCOND*(internal)
BCzF target instruction
BCzF
Delay slot instruction
SYSCLK
CPCOND detection
(a) Full-speed bus mode
F D E M W
F D E M W
F D E M W
(b) Half-speed bus mode
Processor clock
CPCOND*(external)
BCzF target instruction
BCzF
Delay slot instruction
SYSCLK
CPCOND detection
F D E M W
F D E M W
F D E M W
CPCOND*(internal)
Figure 2-6 CPCOND* signal synchronization