Filter
Top Products
Architecture
50
6.2 Exception Processing Registers
The system control coprocessor (CP0) has seven registers for exception processing, shown in Figure 6-1.
(a) Cause register
Indicates the nature of the most recent exception.
(b) EPC (Exception Program Counter) register
Holds the program counter at the time the exception occurred, indicating the address where processing
is to resume after exception processing is completed.
(c) Status register
Holds the operating mode status (user mode or kernel mode), interrupt mask status, diagnostic status
and other such information.
(d) BadVAddr (Bad Virtual Address) register
Holds the most recent virtual address for which a virtual address translation error occurred.
(e) PRId (Processor Revision Identifier) register
Shows the revision number of the R3900 Processor Core.
(f) Cache register
Controls the instruction cache (reserved) and the data cache auto-lock bits.
Note : In addition to the above exception processing registers, the CP0 registers include a Debug and DEPC
register for use in debugging. See chapter 8 for detail.
Figure 6-1. Exception processing registers
BadVAddr
Config
Status
EPC
PRId
Cache
Cause