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2.3 Instruction Set Overview
All R3900 Processor Core instructions are 32 bits in length. There are three instruction formats: immediate
(I-type), jump (J-type) and register (R-type), as shown in Figure 2-4. Having just three instruction formats
simplifies instruction decoding. If more complex functions or addressing modes are required, they can be
produced with the compiler using combinations of the instructions.
op Operation code (6 bits)
rs Source register (5 bits)
rt Target (source or destination) register, or branch condition (5 bits)
rd Destination register (5 bits)
immediate Immediate, branch displacement, address displacement (16 bits)
target Branch target address (26 bits)
sa Shift amount (5 bits)
funct Function (6 bits)
Figure 2-4. Instruction formats and subfield mnemonics
immediatertrsop
31 26 25 21 20 16 15 0
targetop
31 26 25 0
functrd sartrsop
31 26 25 21 20 16 15 11 10 6 5 0
R-type (Register)
J-type (Jump)
I-type (Immediate)