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Architecture
14
Table 2-2(cont.). Instructions supported by MIPS R-Series processors (ISA)
Instruction Description
(Shift)
SLL Shift Left Logical
SRL Shift Right Logical
SRA Shift Right Arithmetic
SLLV Shift Left Logical Variable
SRLV Shift Right Logical Variable
SRAV Shift Right Arithmetic Variable
(Multiply/Divide)
MULT Multiply
MULTU Multiply Unsigned
DIV Divide
DIVU Divide Unsigned
MFHI Move from HI
MTHI Move to HI
MFLO Move from LO
MTLO Move to LO
Jump/Branch Instructions
J Jump
JAL Jump And Link
JR Jump Register
JALR Jump And Link Register
BEQ Branch on Equal
BNE Branch on Not Equal
BLEZ Branch on Less than or Equal to Zero
BGTZ Branch on Greater Than Zero
BLTZ Branch on Less Than Zero
BGEZ Branch on Greater than or Equal to Zero
BLTZAL Branch on Less Than Zero And Link
BGEZAL Branch on Greater than or Equal to Zero And Link
Coprocessor Instructions
MTCz Move to Coprocessor z
MFCz Move from Coprocessor z
CTCz Move Control Word to Coprocessor z
CFCz Move control Word from Coprocessor z
COPz Coprocessor Operation z
BCzT Branch on Coprocessor z True
BCzF Branch on Coprocessor z False
Special Instructions
SYSCALL System Call
BREAK Breakpoint