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MADDU Multiply/Add Unsigned MADDU
31 26 25 21 20 16 15 11 10 6 5 0
MADD/MADDU
011100
rs rt rd
0
00000
MADDU
000001
6 5 5 5 5 6
Format :
MADDU rs, rt
MADDU rd, rs, rt
Description :
Multiplies the contents of general registers rs and rt, treating both values as unsigned , and puts the
double-word result in special registers HI and LO. An overflow exception is never raised.
The low-order word of the multiplication result is put in general register rd and in special register
LO, whereas the high-order word of the result is put in special register HI.
If rd is omitted in assembly language, 0 is used as the default value. To guarantee correct operation
even if an interrupt occurs, neither of the two instructions following MADDU should be DIV or
DIVU instructions which the HI and LO register contents.
Operation :
T:
t ← (HI
||
LO)
+ (0 || GPR[rs])*( 0 || GPR[rt])
LO ← t
31..2
HI ← t
63..32
GPR[rd] ← t
31..0
Exceptions :
None