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8085A18085A·2
A.C. CHARACTERISTICS (Continued)
Symbol Parameter
8085A(2)
8085A·2(2)
Min.
Max. Min.
tRAE
Trailing Edge
of
READ
to
Re·Enabling
150
90
of
Address
tRD
READ
(or INTA)
to
Valid Data
300
tRV
Control
Trailing Edge
to
leading
Edge
400
220
of
Next Control
tRDH
Data Hold Time After
READ
INTA(7)
0 0
tRYH
READY Hold Time
0 0
tRYS
READY Setup Time
to
leading
Edge
110
100
of
ClK
tWD
Data
Valid After Trailing Edge
of
WRITE
100
60
tWDl
lEADING
Edge
of
WRITE
to
Data Valid
40
NOTES:
1.
Aa-A15
address Specs apply
to
101M,
So'
and
S1
except
Aa-A15
are undefined during T
4-T
6
of
OF cycle
whereas
101M,
So'
andS
1
are stable.
2.
Test conditions:
tCYC
= 320ns (8085A)/200 ns (8085A-2); CL = 150 pF.
3.
For all
output
timing
where
CL
= 150pF use the following correction factors:
25pF
..
CL
< 150pF:
-0.10ns/pF
150pF <
CL"
300pF:
+0.30ns/pF
4.
Output
timings
are measured with purely capacitive load.
Max.
150
20
5.
All
timings
are measured at
output
votage V
L
= 0.8V,
VH
= 2.0V, and 1.5V with
20
ns rise and fall time
on
inputs.
6.
To
calculate
timing
specifications
at other values
of
tCYC
use Table
7.
7.
Data hold time is guaranteed under all loading conditions.
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
"=X
)C
2.0 2.0
'?
TEST
POINTS
<
0.8 0.8
0.45
A.C. TESTING: INPUTS ARE DRIVEN
AT
2.4V FOR A LOGIC
"1"
AND 0.45V FOR
A LOGIC
"0."
TIMING MEASUREMENTS ARE MADE
AT
2.0V FOR A LOGIC
"1"
AND
O.SV
FOR A LOGIC
"0."
6-29
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
1"'""'"
TEST
C
L
= 150 pF
C
L
INCLUDES JIG CAPACITANCE
Units
ns
ns
ns
ns
ns
ns
ns
ns
AFN-01242C