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FUNCTIONAL DESCRIPTION
Figure
2-20
illustrates the
81
cycle generated in
response to
RST
7.5 when a HALT instruction
has
just
been executed and the
CPU
is in the
T
HALT state, with
its
various signals floating.
There are only
two
ways the processor can com-
pletely
exit the T HALT state, as shown in Figure
2-11.
The first way is for
RESET
to
occur, which
always forces the 8085A
to
T RESET. The second
way
to
exit
T HALT permanently is for a valid in-
terrupt
to
occur, which will cause the
CPU
to
disable further interrupts by resetting INTE FF,
and
to
then proceed-to
M1
•
T1
of
-the
next in-
struction. When the HOLD input is activated,
the
CPU
will exit T HALT for the duration
of
T HOLD
and then return
to
T HALT.
M1
(OF) M2 (HALT)
SIGNALS
T3 T4
T1
THAlT THAlT
ClK
V-
V-
\J
li\
Lr
RST
7.5
~
[>--
T1
In
Figure
2-20
the
RST
7.5
line is pulsed during
T HALT. Since
RST
7.5
is a rising-edge-triggered
interrupt,
it
will set
an
internal latch which is
sampled during CLK =
"1"
of
every T HALT state
(as
well as during CLK =
"1"
two
T states
before any
M1
•
T1')
The
fact
that the latched in-
terrupt was high (assuming that INTE FF = 1
and the
RST
7.5
mask =
0)
will force the
CPU
to
exit the T
HALT state at the end
of
the next CLK
period, and to enter
M1
• T
1
.
This
completes our analysis
of
the timing
of
each
of
the seven types
of
machine cycles.
M1
(81)
M2(MW)
T2
T3 T4
T5 T6
T1
T2
V
V-
U
V
u u u
U-
~
101M
1,--
r--_.lf
\
51,
SO
\
II
AS·A15
(PC·1)H
~
~--
1----
K
PCH
IN
OUT
~
I---
~--
8
~--
ADO·AD7
HALT
1--_.
1----
pel
---
t---
ALE
r\
n
INTA
RD
U
~--
r..---
V
WR
~--
---V
READY
\
~
~
~
FIGURE 2·20 HALT STATE AND BUS IDLE MACHINE CYCLE
RST
7.S TERMINATES T HALT STATE
2-16
D<
X (SP·1)H '
OUT
~
E
1---
---
---
'r\
L
I