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MCS-85™ APPLICATIONS
Basic operation, for a block move, is
that
the
CPU
loads the 8257 with the
starting
address
of
the source block and the length *
of
the block in-
to
Channel
O.
Channel 1 is programmed with
the
starting location
of
the destination block and
the
length. A bit in Port C
of
the 8255 is set by
the
CPU
which initiates a DMA request on
Channels 0 and
1.
Because the 8257 is initial-
ized
to
the
rotating priority mode, the
first
DMA
cycle is from Channel 0 which latches the
data
from the'
first
location
of
the source block
into
the 8212. The second cycle will be from Channel
1 which will store the latched data
into
the
first
location
of
the destination block. The next cycle
will
return to Channel 0 and the sequence will
start over again until the length (terminal count)
is reached. Programming the 8257 stop bit in-
sures
that
each channel will be disabled when
its respective
terminal count is reached.
This
configuration
also supports a block fill.
DMA Channel 0 point.s to a location containing
the
fill value and has a length
of
one. Channel 1
points
to
the starting location
of
the destination
block and contains the length. When the se-
quence is initiated the
value will be loaded
into
the
latch
by Channel
O.
Channel 0 reaches
TC
and is disabled. Priority rotates
to
Channel 1
which
will repeatedly write
into
the destination
block
the
value stored in the latch until
TC
is
reached.
Block search operations use the 8-bit compara-
tor
and Ports A & B
of
the 8255 and Channel 2
of
the 8257. The
CPU
loads Port B with
the
search
value and the DMA channel
with
the
search
area (starting address and
length). A Port C
bit
initiates
the DMA READ
r~quest.
Channel 2
DMA Acknowledge sets Port A
of
the 8255 up as
the receiver for the DMA READ
cycle by
multiplexing
Ao,
A
1
,
and
CS.
Each cycle
of
the
DMA then loads Port A with the value
of
the
-(The value loaded
into
the low-order 14-bits
of
the
terminal
count
register
specifies
the
number
of
DMA
cycles
minus
one before the
Terminal Count
(TC)
output
is activated. For instance, a terminal
count
of
0 would cause the
TC
output
to
be active in the first DMA
cycle
for
that
channel.
In
general,
if
Length = the number
of
desired DMA cycles, load the value Length-1
into
the
low-order
14-bits
of
the
terminal
count
register.)
A'-7
pointed-to location in the block. When Port A
equals Port
B,
the output
of
the
cqmparator
will
gate
off
the DMA request. The requesting pro-
gram can now read the
Channel 2 address
which is pointing
to
the search value plus one.
However,
if
the
status
register
of
the
8257 in-
dicates
that
TC
of
Channel 2 has been reached,
then no
match
was found.
RST
7
On
the 8080Al8228 system
if
one tied INTA
out
of
the 8228
to
+
12
volts through a 1
KO
resistor,
the 8228
would generate a
RST
7
instruction
to
the 8080A upon interrupt. This was a very inex-
pensive mechanism.
The
8085A has expanded
this
facility
with
the
RST
5.5, 6.5,
7.5
inputs but is not
compatible
with the
RST
7 generated by the 8228. (Figure
5)
To maintain
this
compatibility
it
can be achieved
by adding an 8212 which
will force a
RST
7 in-
struction
into
the bus upon interrupt acknowl-
edge (INTA). (Figure
6)
RESTART VECTOR
LOCATION
RST 7
38'6
RST 5.5
2C'6
RST 6.5
34'6
RST 7.5
3C'6
TRAP
24'6
FIGURE
5_
ADDITIONAL 808SA INTERRUPTS
- RST7.5
INTR-"RST7"
DB2
STB
FIGURE
6.
808SA "RST 7" IMPLEMENTATION