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FUNCTIONAL DESCRIPTION
SIGNAL
eLK
101M,
S1,SO
ALE
FIGURE 2·13 OPCODE FETCH MACHINE CYCLE (OF
DCX
INSTRUCTION)
During T 5 and T 6, of
DCX,
the
CPU
will decre-
ment the designated register.
Since the
As-A15
lines are driven
by
the address latch circuits,
which are part
of
the incrementerldecrementer
logic, the
Aa-A15
lines may change during T 5 and
T
6. Because the value
of
As-A15
can vary during
T
4-T
6,
it
is most important that all memory and
1/0
devices
on...!De
system bus
qua~
their
selection with
RD.
If
they don't use
RD,
they
may be
spuriously selected. Moreover, with a
linear selection technique (Chapter
3),
two
or
more devices
could
be
simultaneously enabled,
which could be potentially damaging. The
generation of spurious addresses can
also oc-
cur momentarily at address bus
transitional
periods in T
1
. Therefore, the selection of all
memolY.!.nd
1/0
devices must
be
qualified with
AD
or
WR.
Many new memory devices like the
8155
and
8355
have the
RD
input that internally
is used
to
enable the data bus outputs, remov-
ing the need for
externally qualifying the chip
enable input with
RD.
Figure
2-14
is identical
to
Figure
2-13
with one
exception, which is the use of the
READY
line.
As we can see in Figure
2-11,
when the
CPU
is in
T2,
it
examines the state
of
the
READY
line.
If
the
READY
line is high, the
CPU
will proceed
to
T 3 and finish executing the instruction. If the
READY
line is low, however, the
CPU
will enter
T
WAIT
and stay there indefinitely until
READY
goes high. When the
READY
line does go high,
the
CPU
will exit T
WAIT
and enter T
3,
in order
to
complete the machine cycle.
As
shown in
2-10
Figure
2-14,
the external effect of using the
READY
line is
to
preserve the exact state
of
the
processor
signals at the end
ofT
2 for
an
integral
number
01..
clock periods, before finishing the
machine
Gycle.
This
"stretching"
of the system
timing has the further effect of increasing the
allowabl~
access time for memory or
1/0
devices.
By
inserting T
WAIT
states, the 8085A
can
accommodate
even
the
slowest
of
memories. Another common use of the
READY
line is
to
singe-step the processor with a
manual switch.
2.3.2 Read Cycle Timing
MEMORY READ (MR):
Figure
2-15
shows the timing of two successive
MEMORY
READ
(MR)
machine cycles, the first
without a T
WAIT
state and the second with one
TWAIT
state. The timing during T
1
-T
3
is
absolute-
ly identical
to the
OPCODE
FETCH
machine cy-
cle, with the exception that the status sent out
during
T1
is
101M
=
0,
S1
=
1,
SO
=
0,
identify-
ing the
cycles as a
READ
from a memory loca-
tion. This differs from Figure
2-13
only in that
SO
= 1 for
an
OF cycle, identifying that cycle as an
OPCODE
FETCH
operation. Otherwise, the
two
cycles are identical during T
1
-T3'
A second difference occurs at the end
of
T
3.
As
shown in Figure
2-11,
the
CPU
always goes to T 4
from T 3 during M
1
, which is
always
an
OF cycle.
During all other machine cycles, the
CPU
will
always go from T
3
.
to
T1
of
the next machine
cycle.