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THE INSTRUCTION SET
5.6.4 Branch Group
This group
of
instructions alter normal sequen-
tial program flow.
Condition
flags are
not
affected by any instruc-
tion in
this
group.
The two types
of
branch instructions are uncon-
ditional
and
conditional.
Unconditional
transfers simply perform the specified opera-
tion on register
PC
(the program counter). Con-
ditional transfers examine the status
of
one
of
the four processor flags
to
determine
if
the
specified branch is
to
be executed. The condi-
tions that may
be
specified are as follows:
CONDITION
CCC
NZ-
not zero
(Z
=
0)
000
Z-
zero
(Z
=
1)
001
NC-
no carry
(CY
=
0)
010
C-
carry
(CY
=
1)
011
Po-
parity odd
(P
=
0)
100
PE-
parity even
(P
=
1)
101
P-
plus
(S
=0)
110
M-
minus
(S
=
1)
111
JMP addr (Jump)
(PC)
- (byte
3)
(byte
2)
Control is transferred
to
the instruction
whose address is specified in byte 3 and
byte 2
of
the current instruction.
I
1 1
I
0
1
0 I 0
10
1
low-order addr
high-order addr
Cycles: 3
States:
Addressing:
10
immediate
none
Flags:
I
1 1
*AII mnemonics
copyrighted©lntel
Corporation
1976.
5-13
Jcondition addr (Conditional jump)
If
(CCC),
1
(PC)
- (byte
3)
(byte
2)
If the specified condition is true, control is
transferred
to
the instruction whose ad-
dress is specified in byte 3 and byte 2
of
the
current instruciton; otherwise,
control con-
tinues sequentially.
I 1
I
c I C I C I a
I 1 I 0
low-order
addr
high-order addr
Cycles: 2/3
(8085),
3
(8080)
States: 7/10
(8085),
10
(8080)
Addressing: immediate
Flags: none
CALL addr
(Call)
1
«SP)
- 1) -
(PCH)
«SP)
-
2)
- (PCl)
(SP)
-
(SP)
- 2
(PC)
- (byte
3)
(byte
2)
The high-order eight
bits
of
the next in-
struction
address are moved
to
the
memory location whose address is one
less than the content
of
register
SP.
The
low-order eight bits
of
the next instruction
address are moved
to
the memory location
whose address is two
less than the content
of
register
SP.
The content
of
register
SP
is
decremented by
2.
Control is transferred
to
the instruction whose address is specified
in byte 3 and byte 2
of
the current instruc-
tion.
I
1
I
o I 0 I 1
I
I
0 I 1
1
low-order addr
high-order addr
Cycles: 5
States:
18
(8085),
17
(8080)
immediatel
Addressing: reg. indirect
Flags: none