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INTRODUCTION TO
MCS-85™
SYSTEM PERFORMANCE
The true benchmark
of
any microcomputer-
based system is the amount of tasks
that
can
be performed by the system in a given period
of
time. Increasing speed
of
CPU
instruction ex-
ecution has been the common approach
to
in-
creasing system throughput but this puts a
greater strain on the memory access require-
ment and bus operation than is
usually prac-
tical
for
most applications. A much more
desirable method would be
to
distribute the
task-load
to
peripheral devices.
DISTRIBUTED PROCESSING
The concept
of
distributed task processing is
not new
to
the computer deSigner, but until
recently
little
if
any task distribution was
available to the microcomputer user. The use of
the
n~w
programmable MCS-80/85 peripherals
can
rel:leve
the central processor
of
many
of
the
bookk~ping
I/O
and timing tasks that would
otherwise have
to
be handled by system soft-
ware.
INSTRUCTION CYCLE/ACCESS TIME
The basic instruction cycle
of
the 8085A is 1.3
microseconds, the same speed as the 8080A-1.
A close look at the MCS-85 bus operation shows
that the access requirement for this speed is
only 575 nanoseconds. The MCS-80 access
re-
quirements for
this
speed would be under 300
nanoseconds. This illustrates the
efficiency
and improved timing margins of the MCS-85 bus
structure.
The
new
8085A-2, a high-speed
selected version
of
the 8085A with a
.8
micro-
second instruction cycle, provides a
60% per-
formance improvement over the standard
8085A.
CONCLUSIONS: THROUGHPUT/COST
•
When a total system throughput/cost analysis
is taken, the
MCS-85 system with its advanced
processor
will yield the most cost-effective,
reliable and producible system.
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20
15
10
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r l
1
o
1973
\
\
\
1974
I/O
1975
YEAR
8085A
CPU
1976
---
1977
1978
MEMORY