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FUNCTIONAL DESCRIPTION
2.3.5 Bus Idle (BI) and HALT State
Most
machine
cycles
of
the
SOS5A
are
associated with either a
READ
or
WRITE opera-
tion. There are
two
exceptions
to
this
rule. The
first
exception takes place during
M2
and
M3
of
the DAD instruction. The
SOS5A
requires six in-
ternal
T states
to
execute a DAD instruciton,
but
it
is
not desirable
to
have
M1
be ten (four
normal plus six extra)· states long. Therefore,
the
CPU
generates two extra machine cycles
that
do
not
access either the memory or the 1/0.
These cycles are referred
to
as
BUS
IDLE
(BI)
machine cycles.
In
the case
of
DAD,
they are
identical
to
MR
cycles except
that
RD
remains
high and ALE is not generated. Note that
READY
is
ignored during
M2
and
M3
of
DAD.
SIGNALS
M
l
I
0F
)
T3
T4
Tl
T2
ClK
V\
Lr
\F
Lr
RST
7.5
A:::.
>-
~
101M
I
SI,
so
C
A8'A15
IPC·I)H
)(
PCH
~
IN
OUT
~
~--
E
)---
AD
O
·AD
7
~
ALE
1\
INTA
RD
U
WI!
READY
\
>
The other time when the
BUS
IDLE machine cy-
cle
occurs is during the internal opcode genera-
tion for the
RST
or TRAP interrupts. Figure 2-19
illustrates the
BI
cycle generated in response
to
RST
7.5.
Since
this
interrupt is rising-edge-
triggered,
it
sets an internal latch; that latch
is
sampled
at
the falling edge
of
the next
to
the
last T-state
of
the previous instruction. At
this
pOint the
CPU
must generate
its
own internal
RESTART
instruction which will (in subsequent
machine
cycles) cause the processor
to
push
the program counter
on
the
stack
and
to
vector
to
location 3CH. To do this,
it
executes an OF
machine cycle
without
issuing
RD,
generating
the
RESTART
opcode instead.
After
M
1
, the
CPU
continues
execution
normally
in
all
respects except
that
the state of the READY
line is ignored during the
BI
cycle.
MllBII
M2
IMW
)
T3
T4
T5
T6
Tl
T2
Lr
U-U-U-U-
U
\.
X
ISP·l)H
OUT
IN
--
---
---
--
E
K=:
n
L
~
I
~
FIGURE 2·19
RST
7.5
BUS
IDLE MACHINE CYCLE
2-15