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ARCHITECTURE OF THE 8080
CPU
The
8080
CPU consists
of
the
following functional
units:
• Register array
and
address logic
•
Arithmetic
and
logic
unit
(ALU)
• Instruction register and
control
section
• Bi-directional,
3-state
data
bus
buffer
Figure 4·2 illustrates
the
functional blocks
within
the
8080
CPU.
Registers:
The register section consists
of
a static RAM array
organized
into
six
16·bit
registers:
• Program
counter
(PC)
•
Stac::k
pointer
(SP)
• Six
8-bit general purpose registers arranged
in
pairs,
referred
to
as B,C; D,E; and H,L
•
A
temporary
register pair called W,Z
The program
counter
maintains
the
memory
address
of
the
next
program instruction and
is
incremented
auto-
POWER
1-
+12V
SUPPLIES _ +5V
_-5V
-GND
(8 BITI
INTERNAL
DATA
BUS
Figure
4-2.
8080
CPU Functional Block Diagram
matically during every
instruction
fetch.
The
stack
pointer
maintains
the
address
of
the
next
available stack location
in
memory.
The
stack
pointer
can be initialized
to
use
any
portion
of
read·write
memory
as a stack.
The
stack
pointer
is
decremented
when
data
is
"pushed"
onto
the
stack
and
incremented
when
data
is
"popped"
off
the
stack (Le.,
the
stack grows
"downward").
The
six general purpose registers can be used
either
as
single registers (8·bit)
or
as register pairs
06·bit).
The
temporary
register pair, W,Z,
is
not
program addressable
and
is
only
used for
the
internal
execution
of
instructions.
Eight-bit
data
bytes
can
~e
transferred
between
the
internal
bus
and
the
register
array
via
the
register-select
multiplexer. Sixteen-bit transfers can proceed
between
the
register array and
the
address latch
or
the
incrementer
/
decrementer
circuit.
The
address latch receives
data
from
any
of
the
four
register pairs and drives
the
16
address
output
buffers (AO-A1Sl. as well as
the
incrementerl
decrementer
circu it.
The
incrementer
/decrementer
circu it
receives
data
from
the
address latch and sends it
to
the
register array.
The
16-bit
data
can be
increm~nted
or
decremented
or
simply transferred between registers.
BI·DIRECTIONAL
DATA
BUS
(81
(81
INSTRUCTION
D
(81
(81
DECODER
AND
MACHINE
CYCLE
ENCODING
TIMING
AND
CONTROL
4-2
REG.
H
(el
REG.
STACK POINTER
PROGRAM COUNTER
A
15
•
Ao
ADDRESS
BUS
(81
REGISTER
ARRAY
1161
1161