Intel MCS-80/85 Computer Hardware User Manual


 
FUNCTIONAL DESCRIPTION
logical choices, since they both force the pro-
cessor
to
push the contents
of
the program
counter onto the stack before jumping
to
a new
location.
In
Figure
2-17
it
is assumed that a
CALL opcode is sent
to
the
CPU
during M
1
The
CALL opcode could have been placed there
bya
device like the 8259 programmable interrupt
controller.
After receiving the opcode, the processor then
decodes
it
and determines, in this case, that the
CALL instruction requires two more bytes. The
CPU
therefore performs a second INA cycle
(M2)
to
access the second byte of the instruction
from the
8259. The timing of this cycle is iden-
tical
to
M
1
,
except that
it
has only three
.T
states.
M2
is followed by another INA cycle
(M3)
to
access the third byte
of
the CALL instruction
from the
8259.
M3
(INA)
SIGNAL
Tl
T2
T3
Tl
M4(MW)
T2
Now that the
CPU
has accessed the entire in-
struction used
to
acknowledge the interrupt,
it
will execute that instruction
..
Note that any in-
struction could
be
used (except
EI
or
01,
the in-·
structions which enable
or
disable interrupts),
but the
RESTART
and CALL instructions are the
most logical choices. Also notice that the
CPU
inhibited the incrementing of the program
counter
(PC)
during the three INA cycles, so
that the correct
PC
value can
be
pushed onto
the stack during
M4
and
M5'
During
M4
and M
s
, the
CPU
performs MEMORY
WRITE
machine cycles
to
write the upper and
then lower bytes
of
the
PC
onto the top of the
stack. The
CPU
then places the two bytes ac-
c,essed
in
M2
and
M3
into the lower and upper
bytes
of
the
PC.
This has the effect
of
jumping
the execution of the program
to
the location
specified by the CALL instruction.
MS(MW)
Ml
(OF)
T3
Tl
T2
T3
Tl
T2
ClK
V V
V'
lJ'
V V
V V V
V
U-
INTR
1---
-
INTA
\\
IOIM,Sl,SO
[X
(1,1,1)
oc
(0,0,1)
D<
A
S
·A
1S
[X
PCH
IX
(SP·l)H
)(
OUT
IN
OUT
OUT
OUT
AO
O
·A0
7
k=:
X 0
0
.0
7
(B3) >
E
0
0
.0
7
(PCH)
E
ALE
r\
"
Jf\.
AD
WR
FIGURE 2·18 INTERRUPT ACKNOWLEDGE MACHINE CYCLES
(WITH CALL INSTRUCTION IN RESPONSE TO INTR)
2·14
(0,0,1)
X
(0,1,1)
(SP·2)H
X
PCH(B3)
OUT
OUT
0
0
.0
7
(PCL)
K::
K
V\
L