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11
INTERRUPTS
I
!
RST
7.5
RST6.5
RST
5.5
X,
X2
r
TRAP
SERIAL
DATA
LINES
~
'!
r
SIO
SOO
8085A
CPU
101
!
t t
RESET
IN
SI
SO
CLK
HOLD
INTR
J!1j
M I
RESET
AO
o
----
---ADl
As-------A,5
ALE
1
WR
1
ROY
OUT
HLDA
IfmI
ALE
AD
Wii
IIOIM
READY
CLK
RESET
HOLD
HLDA
INTR
INTA
11
1
TES
ROM
2K
BY
256 BY
llNTE
48·BIT
16·BIT
41NTE
2SERI
TES RAM
RVAL
TlMERIEVENT COUNTER
I/O
PORTS
I/O·ST ATUS
PORT
RRUPT LEVELS
AL
I/O LINES
+5V
L
Il
PORT A
I
I
PAO-- - -
----PAl
I
PORT C
I
J
PCO-
- - - -
--PCs
I
PORT B
I
1
POo-
- -
:...
- - - -POl
8156
RAM
-I/O -
TIMER/COUNTER
(256
x
81
101
iili
M
ADD·
- - - - - -
-ADl
CE
ALE
I
Wii
RESET
1
1
CE
I
Ag
I
RESETI
ROY
WR
A,o
As
CLK
101M
J!1j
ALE
ADo-------ADl
CE
8355
ROM
-
I/O
8755A
EPROM
-
I/O
2K
X 8
PAo----------PAl
POo- - - - - - - - - .
P0
7
I
I
I
PORT A
II
1 J I
1
PORT B
J
I
Figure
1·1.
MCS·SS™
Basic
System
1-10
TIMER
N
-I
-
TIMER
OUT
}
ADR
DATA
}
ADR
-
-
CONTROL
-