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CP3BT26
GCMTCH The Global Call Match bit is set in slave mode
when the ACBCTL1.GCMEN bit is set and the
address byte (the first byte transferred after a
Start Condition) is 00h. It is cleared by a Start
Condition or repeated Start and Stop Condi-
tion (including illegal Start or Stop Condition).
0 – No global call match occurred.
1 – Global call match occurred.
TSDA The Test SDA bit samples the state of the SDA
signal. This bit can be used while recovering
from an error condition in which the SDA sig-
nal is constantly pulled low by a slave that
went out of sync. This bit is a read-only bit.
Data written to it is ignored.
TGSCL The Toggle SCL bit enables toggling the SCL
signal during error recovery. When the SDA
signal is low, writing 1 to this bit drives the SCL
signal high for one cycle. Writing 1 to TGSCL
when the SDA signal is high is ignored. The bit
is cleared when the clock toggle is completed.
0 – Writing 0 has no effect.
1 – Writing 1 toggles the SDA signal high for
one cycle.
24.3.4 ACB Control Register 1 (ACBCTL1)
The ACBCTL1 register is a byte-wide, read/write register
that configures and controls the ACB module. At reset and
while the module is disabled (ACBCTL2.ENABLE = 0), the
ACBCTL1 register is cleared.
START The Start bit is set to generate a Start Condi-
tion on the ACCESS.bus. The START bit is
cleared when the Start Condition is sent, or
upon detection of a Bus Error
(ACBST.BER = 1). This bit should be set only
when in Master mode, or when requesting
Master mode. If this device is not the active
master of the bus (ACBST.MASTER = 0), set-
ting the START bit generates a Start
Con0dition as soon as the ACCESS.bus is
free (ACBCST.BB = 0). An address send se-
quence should then be performed. If this de-
vice is the active master of the bus
(ACBST.MASTER = 1), when the START bit is
set, a write to the ACBSDA register generates
a Start Condition, then the ACBSDA data is
transmitted as the slave’s address and the re-
quested transfer direction. This case is a re-
peated Start Condition. It may be used to
switch the direction of the data flow between
the master and the slave, or to choose anoth-
er slave device without using a Stop Condition
in between.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Start condition.
STOP The Stop bit in master mode generates a Stop
Condition that completes or aborts the current
message transfer. This bit clears itself after
the Stop condition is issued.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Stop condition.
7 6 5 4 3 2 1 0
STASTRE NMINTE GCMEN ACK Res. INTEN STOP START