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CP3BT26
27.2.8 Counter Register n (COUNTx)
The Counter (COUNTx) registers are word-wide read/write
registers. There are a total of four registers called COUNT1
through COUNT4, one for each of the four timer sub-
systems. Software may read the registers at any time.
Reading the register will return the current value of the
counter. The register may only be written if the counter is
stopped (i.e. if both TxRUN bits associated with a timer sub-
system are clear). The registers are cleared at reset.
27.2.9 Period/Capture Register n (PERCAPx)
The PERCAPx registers are word-wide read/write registers.
There are a total of four registers called PERCAP1 through
PERCAP4, one for each timer subsystem. The registers
hold the period compare value in PWM mode of the counter
value at the time the last associated capture event occurred.
In PWM mode the register is double buffered. If a new peri-
od compare value is written while the counter is running, the
write will not take effect until counter value matches the pre-
vious period compare value or until the counter is stopped.
Reading may take place at any time and will return the most
recent value which was written. The PERCAPx registers are
cleared at reset.
27.2.10 Duty Cycle/Capture Register n (DTYCAPx)
The Duty Cycle/Capture (DTYCAPx) registers are word-
wide read/write registers. There are a total of four registers
called DTYCAP1 through DTYCAP4, one for each timer
subsystem. The registers hold the period compare value in
PWM mode or the counter value at the time the last associ-
ated capture event occurred. In PWM mode, the register is
double buffered. If a new duty cycle compare value is written
while the counter is running, the write will not take effect un-
til the counter value matches the previous period compare
value or until the counter is stopped. The update takes effect
on period boundaries only. Reading may take place at any
time and will return the most recent value which was written.
The DTYCAPx registers are cleared at reset.
15 0
CNTx
15 0
PCAPx
15 0
DCAPx