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CP3BT26
Figure 131. Early Write Between Normal Read Cycles (No Wait States)
T1 T2 T1 T2 T3 T1 T2
A[21:0]
A22 ('13 only)
CLK
Normal Read Normal ReadEarly Write
SELx
D[15:0]
In InOut
t
4
t
4
,
t
12
SELy
(y ≠ x)
RD
WR[1:0]
t
5
,
t
12
t
5
,
t
12
t
5
,
t
12
t
8
,
t
12
t
3
t
9
t
5
,
t
12
t
5
,
t
12
t
6
,
t
13
t
5
,
t
12
t
6
,
t
13
t
2
t
1
Bus State
DS124