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CP3BT26
Figure 132. Late Write Between Normal Read Cycles (No Wait States)
T1 T2 T1 T2 T1 T2
CLK
SELx
D[15:0]
In InOut
(y ≠ x)
RD
Normal Read Normal ReadLate Write
t
4
,
t
12
t
5
,
t
12
t
5
,
t
12
t
5
,
t
12
t
5
,
t
12
t
8
,
t
12
t
3
t
11
t
5
,
t
12
t
6
,
t
13
t
6
,
t
13
t
5
,
t
12
t
10
t
9
t
4
,
t
12
SELy
(y ≠ x)
WR[1:0]
A[21:0]
A22 ('13 only)
Bus State
DS125