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CP3BT26
Figure 135. Early Write Between Fast Read Cycles
T
idle
T1-2 T1 T1T2 T3 T1-2
Fast Read Early Write
CLK
SELx
SELy
WR[1:0]
D[15:0]
(y ≠ x)
(y ≠ x)
RD
Fast Read
t
5
,
t
12
t
5
,
t
12
t
2
t
1
t
5
,
t
12
t
5
,
t
12
t
4
,
t
12
t
4
A[21:0]
A22 ('13 only)
Bus State
DS128
In InOut