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CP3BT26
30.8 UART TIMING
Figure 114. UART Asynchronous Mode Timing
Table 85 UART Signals
Symbol
Figure
Description Reference Min (ns) Max (ns)
UART Input Signals
t
Is
114
Input setup time
RXD (asynchronous mode)
Before Rising Edge (RE)
on CLK
-
t
Ih
114
Input hold time
RXD (asynchronous mode)
After RE on CLK -
UART Output Signals
t
COv1
114
TXD output valid (all signals with
propagation delay from CLK RE)
After RE on CLK -
t
TXD
114 TXD output valid After RE on CLK - 40
CLK
TXD
RXD
1
t
COv1
t
lS
t
lH
t
COv1
11222111222
DS098