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FLL+ Clock Module Operation
4-5FLL+ Clock Module
4.2 FLL+ Clock Module Operation
After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the
ACLK frequency. When a 32,768-Hz crystal is used for ACLK, MCLK and
SMCLK will stabilize to 1.048576 MHz.
Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure
the MSP430 operating modes and enable or disable components of the FLL+
clock module. See Chapter System Resets, Interrupts and Operating Modes.
The SCFQCTL, SCFI0, SCFI1, FLL_CTL0, and FLL_CTL1 registers configure
the FLL+ clock module. The FLL+ can be configured or reconfigured by
software at any time during program execution.
Example, MCLK = 64 × ACLK = 2097152
BIC #GIE,SR ; Disable interrupts
MOV.B #(64−1),&SCFQTL ; MCLK = 64 * ACLK, DCOPLUS=0
MOV.B #FN_2,&SCFIO ; Select DCO range
BIS #GIE,SR ; Enable interrupts
4.2.1 FLL+ Clock features for Low-Power Applications
Conflicting requirements typically exist in battery powered MSP430x4xx
applications:
- Low clock frequency for energy conservation and time keeping
- High clock frequency for fast reaction to events and fast burst processing
capability
- Clock stability over operating temperature and supply voltage
The FLL+ clock module addresses the above conflicting requirements by
allowing the user to select from the three available clock signals: ACLK, MCLK,
and SMCLK. For optimal low-power performance, the ACLK can be
configured to oscillate with a low-power 32,786-Hz watch-crystal, providing a
stable time base for the system and low power stand-by operation. The MCLK
can be configured to operate from the on-chip DCO, stabilized by the FLL, and
can activate when requested by interrupt events.
The digital frequency-locked loop provides decreased start-time and
stabilization delay over an analog phase-locked loop. A phase-locked loop
takes hundreds or thousands of clock cycles to start and stabilize. The FLL
starts immediately at its previous setting.