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ADC12 Introduction
20-3ADC12
Figure 20−1. ADC12 Block Diagram
Sample
and
Hold
Ve
REF+
12−bit SAR
V
R−
−
16 x 12
Memory
Buffer
−
−
16 x 8
Memory
Control
−
V
R+
V
REF+
Ve
REF−
V
REF−
/
ADC12SC
TA1
TB1
TB0
Divider
/1 .. /8
ADC12DIVx
ADC12CLK
ENC
MSC
SHP
SHT0x
SAMPCON
SHI
S/H Convert
Sync
Sample Timer
/4 .. /1024
INCHx
4
A0
A1
A2
A3
A4
A5
A6
A7
ADC12MEM0
ADC12MEM15
ADC12MCTL0
ADC12MCTL15
CSTARTADDx
4
4
SHT1x
CONSEQx
ACLK
MCLK
SMCLK
ADC12SSELx
ADC12OSC
00
01
10
11
00
01
10
11
SHSx
00
01
10
11
00
01
10
11
ISSH
1
0
0
1
SREF2 01
SREF1
0001
SREF0
10
ADC12ON
BUSY
REFON
INCHx=0Ah
1.5 V or 2.5 V
Reference
on
Ref_x
Ref_x
INCHx=0Bh
11
R
R
0000
1001
1000
0010
0001
0011
0100
0101
0110
0111
1011
1010
0001
1111
1110
1101
1100
REF2_5V
AV
CC
AV
CC
AV
CC
AV
SS
AV
SS
A12
†
A13
†
A14
†
A15
†
†MSP430FG43x devices only