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Hardware Multiplier Operation
7-3Hardware Multiplier
7.2 Hardware Multiplier Operation
The hardware multiplier supports unsigned multiply, signed multiply, unsigned
multiply accumulate, and signed multiply accumulate operations. The type of
operation is selected by the address the first operand is written to.
The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and
three result registers, RESLO, RESHI, and SUMEXT. RESLO stores the low
word of the result, RESHI stores the high word of the result, and SUMEXT
stores information about the result. The result is ready in three MCLK cycles
and can be read with the next instruction after writing to OP2, except when
using an indirect addressing mode to access the result. When using indirect
addressing for the result, a NOP is required before the result is ready.
7.2.1 Operand Registers
The operand one register OP1 has four addresses, shown in Table 7−1, used
to select the multiply mode. Writing the first operand to the desired address
selects the type of multiply operation but does not start any operation. Writing
the second operand to the operand two register OP2 initiates the multiply
operation. Writing OP2 starts the selected operation with the values stored in
OP1 and OP2. The result is written into the three result registers RESLO,
RESHI, and SUMEXT.
Repeated multiply operations may be performed without reloading OP1 if the
OP1 value is used for successive operations. It is not necessary to re-write the
OP1 value to perform the operations.
Table 7−1.OP1 addresses
OP1 Address Register Name Operation
0130h MPY Unsigned multiply
0132h MPYS Signed multiply
0134h MAC Unsigned multiply accumulate
0136h MACS Signed multiply accumulate