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Hardware Multiplier Introduction
7-2 Hardware Multiplier
7.1 Hardware Multiplier Introduction
The hardware multiplier is a peripheral and is not part of the MSP430 CPU.
This means, its activities do not interfere with the CPU activities. The multiplier
registers are peripheral registers that are loaded and read with CPU
instructions.
The hardware multiplier supports:
- Unsigned multiply
- Signed multiply
- Unsigned multiply accumulate
- Signed multiply accumulate
- 16×16 bits, 16×8 bits, 8×16 bits, 8×8 bits
The hardware multiplier block diagram is shown in Figure 7−1.
Figure 7−1. Hardware Multiplier Block Diagram
OP2 138h
16 x 16 Multipiler
32−bit Adder
32−bit Multiplexer
015
15 0
Multiplexer
C
MPY 130h
MPYS 132h
MAC 134h
MACS 136h
RESHI 13Ch
S
SUMEXT 13Eh
OP1
RESLO 13Ah
031
MPY, MPYS MAC, MACS
MACS MPYS
MAC
MPY = 0000
rw
rw
rwrw015 r
Accessible
Register