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FLL+ Clock Module Registers
4-14 FLL+ Clock Module
FLL_CTL0, FLL+ Control Register 0
76543210
DCOPLUS XTS_FLL XCAPxPF XT2OF
†
XT1OF LFOF DCOF
rw−0 rw−0 rw−0 rw−0 r0 r0 r−(1) r−1
† Not present in MSP430x41x, MSP430x42x devices
DCOPLUS
Bit 7 DCO output pre-divider. This bit selects if the DCO output is pre-divided
before sourcing MCLK or SMCLK. The division rate is selected with the
FLL_DIV bits
0 DCO output is divided
1 DCO output is not divided
XTS_FLL
Bit 6 LFTX1 mode select
0 Low frequency mode
1 High frequency mode
XCAPxPF
Bits
5−4
Oscillator capacitor selection. These bits select the effective capacitance
seen by the LFXT1 crystal or resonator when XTS_FLL = 0.
00 ~1 pF
01 ~6 pF
10 ~8 pF
11 ~10 pF
XT2OF
Bit 3 XT2 oscillator fault. Not present in MSP430x41x, MSP430x42x devices.
0 No fault condition present
1 Fault condition present
XT1OF
Bit 2 LFXT1 high frequency oscillator fault
0 No fault condition present
1 Fault condition present
LFOF
Bit 1 LFXT1 low frequency oscillator fault
0 No fault condition present
1 Fault condition present
DCOF
Bit 0 DCO oscillator fault
0 No fault condition present
1 Fault condition present