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Scan IF Operation
24-18 Scan IF
TSM Test Cycles
For calibration purposes, to detect sensor drift, or to measure signals other
than the sensor signals, a test cycle may be inserted between TSM cycles by
setting the SIFTESTD bit. The time between the TSM cycles is not altered by
the test cycle insertion as shown in Figure 24−9. At the end of the test cycle
the SIFTESTD bit is automatically cleared. The TESTDX signal is active during
the test cycle to control input and output channel selection. TESTDX is
generated after the SIFTESTD bit is set and the next TSM sequence
completes.
Figure 24−9. Test Cycle Insertion
TSM Start Signal
(Divided ACLK)
Normal Cycle
Normal
Cycle
Test
Cycle
Normal Cycle
Normal
Cycle
Test
Cycle
SIFTESTD
SIFTESTD set by Software
TSM Active
TESTDX
SIFTESTD automatically cleared