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8-11
Figure 8−5. DMA Burst-Block Transfer State Diagram
2 x MCLK
Reset
Wait for Trigger
Idle
Hold CPU,
Transfer one word/byte
Burst State
(release CPU for 2xMCLK)
[+Trigger AND DMALEVEL = 0 ]
OR
[Trigger=1 AND DMALEVEL=1]
DMAABORT=0
DMAABORT = 1
2 x MCLK
DMAEN = 0
Modify T_SourceAdd
Modify T_DestAdd
Decrement DMAxSZ
[DMADTx = {6, 7}
AND DMAxSZ = 0]
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND Trigger = 0]
[DMADTx = {2, 3}
AND DMAxSZ = 0]
OR
DMAEN = 0
DMAxSZ → T_Size
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMAEN = 0
DMAEN = 1
DMAxSZ > 0
DMAxSZ > 0 AND
a multiple of 4 words/bytes
were transferred
DMAxSZ > 0
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ