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Scan IF Registers
24-43Scan IF
SIFVCC2
Bit 8 Mid-voltage generator
0AV
CC
/2 generator is off
1AV
CC
/2 generator is on if SIFSH = 0
SIFSH
Bit 7 Sample-and-hold enable
0 Sample-and-hold is disabled
1 Sample-and-hold is enabled
SIFTEN
Bit 6 Excitation enable
0 Excitation circuitry is disabled
1 Excitation circuitry is enabled
SIFTCH1x
Bits
5-4
These bits select the comparator input for test channel 1.
00 Comparator input is SIFCH0 when SIFCAX = 0
Comparator input is SIFCI0 when SIFCAX = 1
01 Comparator input is SIFCH1 when SIFCAX = 0
Comparator input is SIFCI1 when SIFCAX = 1
10 Comparator input is SIFCH2 when SIFCAX = 0
Comparator input is SIFCI2 when SIFCAX = 1
11 Comparator input is SIFCH3 when SIFCAX = 0
Comparator input is SIFCI3 when SIFCAX = 1
SIFTCH0x
Bits
3-2
These bits select the comparator input for test channel 0.
00 Comparator input is SIFCH0 when SIFCAX = 0
Comparator input is SIFCI0 when SIFCAX = 1
01 Comparator input is SIFCH1 when SIFCAX = 0
Comparator input is SIFCI1 when SIFCAX = 1
10 Comparator input is SIFCH2 when SIFCAX = 0
Comparator input is SIFCI2 when SIFCAX = 1
11 Comparator input is SIFCH3 when SIFCAX = 0
Comparator input is SIFCI3 when SIFCAX = 1
SIFTCH1
OUT
Bit 1 AFE output for test channel 1
SIFTCH0
OUT
Bit 0 AFE output for test channel 0