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Hardware Multiplier Operation
7-4 Hardware Multiplier
7.2.2 Result Registers
The result low register RESLO holds the lower 16-bits of the calculation result.
The result high register RESHI contents depend on the multiply operation and
are listed in Table 7−2.
Table 7−2.RESHI Contents
Mode RESHI Contents
MPY Upper 16-bits of the result
MPYS The MSB is the sign of the result. The remaining bits are the
upper 15-bits of the result. Two’s complement notation is used
for the result.
MAC Upper 16-bits of the result
MACS
Upper 16-bits of the result. Two’s complement notation is used
for the result.
The sum extension registers SUMEXT contents depend on the multiply
operation and are listed in Table 7−3.
Table 7−3.SUMEXT Contents
Mode SUMEXT
MPY
SUMEXT is always 0000h
MPYS
SUMEXT contains the extended sign of the result
00000h Result was positive or zero
0FFFFh Result was negative
MAC
SUMEXT contains the carry of the result
0000h No carry for result
0001h Result has a carry
MACS
SUMEXT contains the extended sign of the result
00000h Result was positive or zero
0FFFFh Result was negative
MACS Underflow and Overflow
The multiplier does not automatically detect underflow or overflow in the
MACS mode. The accumulator range for positive numbers is 0 to 7FFF FFFFh
and for negative numbers is 0FFFF FFFFh to 8000 0000h. An overflow occurs
when the sum of two negative numbers yields a result that is in the range for
a positive number. An underflow occurs when the sum of two positive numbers
yields a result that is in the range for a negative number. In both of these cases,
the SUMEXT register contains the correct sign of the result, 0FFFFh for
overflow and 0000h for underflow. User software must detect and handle
these conditions appropriately.