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Scan IF Operation
24-17Scan IF
TSM State Clock Source Select
The TSM clock source is individually configurable for each state. The TSM can
be clocked from ACLK or a high frequency clock selected with the SIFACLK
bit. When SIFACLK = 1, ACLK is used for the state, and when SIFACLK = 0,
the high frequency clock is used. The high frequency clock can be sourced
from SMCLK or the TSM internal oscillator, selected by the SIFCLKEN bit. The
high-frequency clock can be divided by 1,2,4 or 8 with SIFDIV1x bits.
A set SIFCLKON bit is used to turn on the selected high frequency clock source
for the duration of the state, when it is not used for the state. If the DCO is
selected as the high frequency clock source, it is automatically turned on,
regardless of the low-power mode settings of the MSP430.
The TSM internal oscillator generates a nominal frequency of 1MHz or 4MHz
selected by the SIFFNOM bit and can be tuned in nominal 5% steps from −40%
to +35% with the SIFCLKFQx. The frequency and the steps differ from
device-to-device. See the device-specific datasheet for parameters.
The TSM internal oscillator frequency can be measured with ACLK. When
SIFCLKEN = 1 and SIFCLKGON = 1 SIFCNT3 is reset, and beginning with the
next rising edge of ACLK, SIFCNT3 counts the clock cycles of the internal
oscillator. SIFCNT3 counts the internal oscillator cycles for one ACLK period
when SIFNOM = 0 and four ACLK periods when SIFNOM = 1. Reading
SIFCNT3 while it is counting will result in reading 01h.
TSM Stop Condition
The last state the TSM is marked with SIFSTOP = 1. The duration of this last
state is always one SIFCLK cycle regardless of the SIFACLK or SIFREPEATx
settings. The SIFIFG1 interrupt flag is set at when the TSM encounters a state
with a set SIFSTOP bit.